Apple II
Technical Notes
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                                                  Developer Technical Support


Apple IIGS
#30:    Apple IIGS Hardware Reference Updates

Revised by:    Rilla Reynolds                                   November 1988
Written by:    Rilla Reynolds                                    October 1987

This Technical Note includes updates to the July 1987 edition of the Apple 
IIGS Hardware Reference, published by Addison-Wesley (Part Number 030-3120-A).  
Please contact Apple II Developer Technical Support at the address listed in 
Apple II Technical Note #0 if you have additional corrections or suggestions 
for this manual.
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Chapter 3:  Memory

    Page 36, Table 3-2, Bits in the State Register:  bit 2, value 1 
    description  should read, "LCBNK2:  If this bit is 1, language-card RAM 
    bank 2 is selected."


Chapter 6:  The Apple Desktop Bus

    Page 130, Table 6-9, Command byte syntax:  The first row in the 
    table should read:

        x     x     x     x     0    0    0    0    Send Reset

    and not

        A(3)  A(2)  A(1)  A(0)  0    0    0    0    Device Reset

    Page 131, Device Reset:  Replace "Device Reset" with "Send Reset."  The 
    paragraph should be:  "When a device receives a Send Reset command, it will 
    clear all pending operations and data, and will initialize to the power-on 
    state.  The Send Reset command is not device-specific; it is sent to all 
    devices simultaneously."

    Pages 138-139, Collision detection:  The fourth sentence in the last 
    paragraph should be:  "By using the Listen register 3 command, the host can 
    move the device with the activator pressed."


Chapter 7:  Built-in I/O Ports and Clock

    Page 146, Table 7-3, Disk-port soft switches:
    $C0E8    Drive disabled
    $C0E9    Drive enabled
    $C0EA    Drive 1 select
    $C0EB    Drive 2 select

    In addition to the corrections listed for Table 7-3, the reference to 
    "spindle motor switches" in the paragraph following the table should be 
    replaced with "drive enable switches."

    The following text and table should also be added:

    The drive enable switches and the drive select switches control the state 
    of the disk port signals DR1 and DR2.  The following table shows the 
    relationship between these.

                 Soft Switches           Disk Port Signals
        $C0E8    $C0E9    $C0EA    $C0EB    DR1    DR2
          1        o        o        o       0      0
          o        1        1        o       1      0
          o        1        o        1       0      1

    1 = asserted state    0 = negated state    o = do not care

    Page 147, The Mode register:  The IWM Mode register is a write-only 
    register, so disregard the advice to use only a read-modify-write 
    instruction sequence when manipulating bits.

    Pages 147-8, Table 7-5, Bits in the Mode register:  Switch the 
    given values and descriptions for bits 1, 2, and 4 as follows:

    Bit    Value    Description
     4       0      7-MHz read-clock speed selected.  Set to 0 for all Apple 
                    IIGS disk accesses.
             1      8-MHz read-clock speed selected.
     2       0      1-second timer selected.  When the current disk drive is 
                    deselected, the drive will remain enabled for 1 second
                    if this bit is set.
             1      1-second timer is not selected.
     1       0      Synchronous handshake protocol selected; for 5.25-inch
                    Apple disk drives.
             1      Asynchronous handshake protocol selected; for all except 
                    5.25-inch Apple disk drives.


Chapter 8:  I/O Expansion Slots

    Page 167, Direct memory access:  DMA bank register location is $C037.


Further Reference:
o    Apple IIGS Hardware Reference

